1. Field of the Invention
This is the National Stage entry of PCT/JP2007/052056 filed on Feb. 6, 2007 which claims priority from Japanese Patent Application No. 2006-027886, filed on Aug. 16, 2007.
The present invention relates to a multilayered wiring structure and a method for manufacturing a multilayered wiring and, more particularly, to a method for manufacturing a multilayered wiring structure and a multilayered wiring having a trench wiring called Damascene structure.
2. Description of the Related Art
Aiming to more sufficiently describe the current technical level relating to the present invention, all of the patents, patent applications, patent publications, scientific articles and so on, which are cited or specified herein, are hereby incorporated by reference in their entirety.
Recent VLSI devices require more than millions of elements to be integrated in a chip of several millimeters square, and thus, it is essential to miniaturize the elements and to manufacture miniaturized and a multilayered wiring. Here, particularly for faster operational velocity of the device, reduction in wiring resistance and interlayer capacitance is a problem of key importance.
For reduction in wiring resistance and interlayer capacitance, a method is used in which copper is employed as a wiring material, and in which a film lower in dielectric constant than a silicon oxide film is employed as an interlayer insulation film
Copper wiring is a most-watched material as a next generation of wiring material for its low resistance and high reliability. However, unlike conventional metal materials, fabrication of copper by dry etching is difficult, and hence, an embedded wiring technology (Damascene method) is conducted. Further, in order to achieve lower interlayer capacitance, a low-k dielectric constant film containing a pore is proposed as a wiring interlayer film. An example of the method for forming low-k dielectric constant film/copper wiring includes a manufacturing method as illustrated in FIG. 12.
First, a MOS transistor 902 is formed on a semiconductor substrate such as a silicon substrate 901; a silicon oxide film 903 is formed as an interlayer insulation film to cover the transistor portion; and then a contact plug 904 that connects the transistor and the wiring portion is formed using tungsten, for example. Next, a silicon carbide-nitride film 905 is formed by means of the CVD method as an etching stopper that prevents the interlayer insulation film from being etched from the upper layers. Further, a porous SiOCH film 906 is formed on the silicon carbide-nitride film 905 by means of, for example, the CVD method as an interlayer insulation film. Here, the typically used porous SiOCH films have a relative dielectric constant of 2.7 or less. Further, a silicon oxide film 907 is formed as a cap layer for the porous SiOCH film. Next, an antireflection film 908 and a resist film 909 are formed on the silicon oxide film 907, so that an opening trench is formed on the resist film by means of the photolithography technique and so on [FIG. 1(a)]. The antireflection film 908, the silicon oxide film 907 and the porous SiOCH film 906 are etched, using the resist film 909 as a mask [FIG. 1(b)], and the resist mask and the antireflection film are removed [FIG. 1(c)]. Subsequently, a silicon carbide-nitride film 905, which is an etching stopper, is etched [FIG. 1(d)]; and a wiring trench 910 is formed to be in contact with the contact plug 904. Then, a bather layer 911 comprising Ta is formed by means of the sputtering method, and further, a copper layer 912 is formed by means of, for example, the sputtering method and the plating method so that the copper layer 912 will be embedded in the wiring trench 910, and the unnecessary portion of the bather and copper layers 91 land 912 is polished and removed by means of the chemical mechanical polishing method (CMP method) whereby a trench wiring 913 is formed [FIG. 1(e)]. Further, a silicon carbide-nitride film 914 is formed as a cap film that inhibits diffusion of copper [FIG. 1(f)]. Then, a required number of layers comprising an interlayer insulation film, a conductive plug and a trench wiring are formed to provide a multilayered wiring.
It is well recognized that in the conventional structure fabricated by means of the above-described process called Damascene manufacturing method, the shorter the interwiring distance is due to the miniaturization, the lower the interwiring insulation is. It is reported that, for example, in the TDDB (Time Dependent Dielectric Breakdown) test in which a voltage is applied to the interwiring to measure the time until the dielectric breakdown occurs, the smaller the size is, the shorter the time until the dielectric breakdown becomes. This requires a technology for ensuring insulation in spite of the smaller size, and hence, several methods are proposed.
The main cause of the TDDB defect is that as shown in FIG. 2, a leakage current passes through the insulation film interface placed at the same height as the Cu-polished surface, and that thereby a short circuit occurs. To inhibit the defect, methods for lowering the height of the insulation film interface with respect to the Cu-polished surface are proposed (For example, see Patent Documents 1 to 3). For example, Patent Document 1 discloses a method in which a silicon nitride film is formed on the interlayer insulation film, and Cu is embedded in a trench that extends through the interlayer insulation film and the silicon nitride film, and then the wiring is polished so that the silicon nitride film is removed by means of dry etching or wet etching. In addition, Patent Document 2 discloses a method in which a Cu wiring is formed in the interlayer insulation film, and then a portion of the interlayer insulation film is removed by means of dry etching or wet etching. Further, Patent Document 3 discloses a method in which a Cu wiring is formed between the interlayer insulation films, and then the surface of an interlayer insulation film is abraded by dry plasma treatment prior to formation of a cap film.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2000-77519    [Patent Document 2] Japanese Laid-open Patent Publication No. 2000-323479    [Patent Document 3] Japanese Laid-open Patent Publication No. 2003-124311